2D+Design+Challenge+2017

= The Story = toc The company Digi-alpha decided to improve their ALU (arithmetic and logic unit) design by speeding up their 32-bit adder. In their original design, the 32-bit adder worked with a clock frequency of about 70 MHz. The company wanted to increase the clock frequency to about 300 MHz. To do this, the 32-bit adder must be able to work in a pipelined stage with a clock period of about 3 ns.

=The Challenge= The company needs to speed up the 32-bit adder of their ALU design so that it can work with a clock period of 3 ns. Their original 32-bit adder design worked with a clock cycle of about 14 ns. This means that the company needs to improve the speed by about five times (5x). Not only that, the company needs to ensure that the 32-bit adder still functions as the original 32-bit adder. To do a thorough hardware verification during the design stage, the chief engineer decided to implement Combinational Equivalence Checking (CEC) using SAT (Satisfiability) technique. The company then has to divide the work into two separate tasks:
 * 1) optimize the original 32-bit adder to work with a clock period of 3 ns.
 * 2) implement CEC using SAT technique to verify the functionality of the optimized hardware design.
 * 3) implement 2-SAT algorithm and test.

=Design= You are tasked to work on both the optimization of the 32-bit adder as well as the software implementation of the CEC-SAT verification. A more detailed guide on the two tasks can be found on the following link.
 * 1) 32-bit Adder optimization
 * 2) CEC-SAT verification software
 * 3) 2-SAT algorithm implementation

Download the following files:
 * JSim Checkoff files for 32-bit adder optimization

=Why is this a 2D+ Challenge?= Below is a cross list that correlates sample tasks in the design challenge with material from various courses. =Milestones= Deliverable 1: You need to submit the optimized design netlist of the 32-bit adder using the JSim and 50.002 Checkoff system. The system will compare for plagiarism or duplicate copy.
 * **Design subtask** || **Techniques from** || **ISTD Subject** ||
 * 32-bit adder optimization || * combinational logic synthesis
 * timing specification || 50.002 Computation Structure ||
 * CEC-SAT verification software || * satisfiability problem
 * DPLL algorithm || 50.001 Introduction to Information Systems and Programming ||
 * SAT Algorithm analysis report || * Algorithm analysis
 * Depth-first search with backtracking
 * Complexity of SAT || 50.004 Introduction to Algorithms ||

Deliverable 2: You need to submit the source code for the CEC-SAT verification software (SAT Solver).

Deliverable 3: You need to submit a short report on the implementation and analysis of your 2-SAT algorithm.

Deliverable 4: You need to demo/present to instructors on your optimized hardware and CEC-SAT Solver. The execution time of your SAT Solver will be tested by our provided .cnf file (about 6000 clauses).

Deliverables 1-3 must be submitted by **Friday, 3rd of November 2017**. Submit on 50.002 eDimension Week 8.

Deliverable 4 (Demo) will be on **Friday, 3rd of November 2017**. Please check your demo schedule.

=Design Evaluation and Reports= The evaluation for the optimized 32-bit adder will be done according to the minimum clock period you can achieve. The table that relates clock period and points you will get can be found on the detailed handout. The maximum point for this task is 10 points.

The software design and implementation for CEC-SAT verification will be graded for 10 points. The table shows the point allocation.

=Consultation Hour= There will be no class during 2D week, however, instructors will come at the following timeslots.
 * ~ Task ||~ Maximum points ||~ Course percentage ||
 * Optimize 32-bit adder ||= 10 || 50.002 (10%) ||
 * CEC-Verification SAT software ||= 10 || 50.001 (10%) ||
 * Algorithm analysis report ||= 10 || 50.004 (10%) ||

50.001 Schedule (Cohort Classroom 10): 50.002 Schedule (Digital Systems Lab - 2.412): 50.004 Schedule:
 * Usual class timings
 * Usual class timings
 * By appointment or email

=Grouping= Each group is 5 - 6 persons. Students are free to form their own groups. Please submit the name of the your group members at the link below by **Sunday, 29th of October 2017**:
 * Submit your group member names

=Competition= The students will compete to design the fastest 32-bit adder and the faster SAT solver. The best team will get a cash prize of $500. The winner will be the team that has the best timing for both point 1 and 2 above.
 * 1) Students can design their 32-bit adder to be working with clock period smaller than 3 ns. The smallest **time** for the speed and chip **area** will be recorded for consideration in the competition.
 * 2) Students will run their SAT solver for 6000 clauses test case provided by the instructor. The shortest time for the SAT solver to finish will be recorded for consideration in the competition.

=Links=
 * Powerpoint slide during briefing
 * Video briefing
 * BC2CNF Converter on the Web
 * FindSolsSAT.jar
 * 2D Winners for ISTD Term 4