I+got+Error+-+a+clock+IOB+or+clock+component+have+been+found+...

I found sometimes although simulation in multisim is successful, I still cannot export the program into the FPGA board.

To solve this error, please follow the steps below:

1. "Transfer" -> "Export to PLD" to open the "PLD Export" Dialog.

2. Click "Next" to "PLD Export - Step 2 of 2".

3. Find "Xilinx user constraint files (*.ucf)" field, and copy the path. 4. Open the .ucf file with any text editor (e.g. Notepad).

5. Find the line corresponding to the error message (i.e. In my case, find the line started with "NET "SW1"").

6. The original line may be like this : **Net "SW1" LOC="J12" | IOSTANDARD = LVCMOS33;** Edit it into the a line like this (i.e. Append "| CLOCK_DEDICATED_ROUTE = FALSE" in the end before the semicolon): **Net "SW1" LOC="J12" | IOSTANDARD = LVCMOS33 | CLOCK_DEDICATED_ROUTE = FALSE;**

7. Save the file with a name of "*.ucf". It is highly recommended that you should not overwrite the original file.

8. Then you can have another try to export your program to FPGA. Remember to change "Xilinx user constraint files (*.ucf)" field to the new .ucf file in "PLD Export - Step 2 of 2" dialog.